SWI3S v1.0

Overview

Truechip's SWI3S Verification IP provides an effective and efficient way to verify the components interfacing with SWI3S interface of an IP and SOC. Truechip's SWI3S VIP is fully compliant to SWI3S Specification version 1.0. The VIP is lightweight with easy plug-and- play interface so that there is no hit on the design cycle time.

Key Benefits

• Available in native System Verilog (UVM/OVM/ VMM) and Verilog
• Unique development methodology to ensure the highest levels of quality
• Availability of Compliance & Regression Test Suites
• 24X5 customer support
• Unique and customizable licensing models
• Exhaustive set of assertions and coverage points with connectivity example for all the components
• Consistency of interface, installation, operation, and documentation across all our VIPs
• Provide complete solution and easy integration in IP and SoC environment

Features

• Fully compliant with the revision 1.0 of the SWI3S Specification.
• Supports topology with one manager–one peripheral as well as multiple peripheral configurations.
• Supports generation of transactions with UVM register model.
• Supports all control and status Commands used in SWI3S.
• Supports all layers in the Command Stack of a SWI3S device.
• Supports all layers in the Payload Stack of a SWI3S device.
• Supports row and column structure in the PHY layer.
• Provide all timing and clock configuration of PHY layer.
• Supports all frequency of audio sampling applications.
• Provide all types and fields of peripheral register.
• Supports Interrupt communication mechanism.
• Supports 8b/10b-Encoding-Decoding mechanism in a Device.
• Support all modes of a Data Port.
• Support the process of all phases and error handling in the Command Transport protocol layer.
• Support all responses of Manager and Peripheral in the Command layer.
• Support CRC16 checking and calculation. Ø Supports Dynamic as well as Static Error Injection and detection scenarios.
  • Error injection in the CRC calculation
  • 8b/10b encoding error
  • Error injection in data scrambling mechanism
  • Invalid data during the transmission of 30-bit PHY calibration blocks
  • Reserved bit field violation checks in the register of peripheral
  • Unknown value checks during transmission of data
• Built in Bus Monitor provides extensive protocol checking.
• On the fly protocol checking using protocol check functions, static and dynamic assertion.
• Built in Coverage analysis.
• Provides a comprehensive user API (callbacks) in Manager and Peripheral
• Graphical analyzer for all Layers to show transactions for easy debugging.

Deliverables

• SWI3S Manager/Peripheral BFM/Agent.
• SWI3S Monitor and Scoreboard.
• Testbench Configurations.
• Test Suite (Available in Source Code).
  • Basic and Directed Protocol Tests.
  • Random Tests.
  • Error Scenario Tests.
  • Assertions & Coverage Tests.
  • Integration Guide, User Manual and Release Notes.